The present invention relates to a non-volatile semiconductor memory device having memory cells based on a stacked gate structure, and to a manufacturing method thereof.
What has hitherto been known as anon-volatile semiconductor memory (EEPROM (Electrically Erasable Programmable Read-Only Memory)) capable of electrically reprogramming data, is a flash memory using memory cells taking a MOS transistor structure based on a stacked structure of a charge-storage layer and a control gate.
FIG. 1 is a plan view showing a NOR type EEPROM using those memory cells. FIGS. 2A and 2B are sectional views taken along the lines A–A′ and B–B′, respectively, in FIG. 1.
Isolation insulating films 102 are buried into a memory cell array area on a silicon substrate 101, thereby defining device forming regions 103 continuous in a y-direction at a predetermined interval in an x-direction. Charge-storage layers 105 are provided via tunnel insulating films 104 on the substrate with the device being thus isolated, and a control gate 108 is provided via a gate-to-gate insulating film 107 on the charge-storage layers 105, thus configuring a memory cell. The charge-storage layer 105 is isolated by the isolation insulating film 102 and thus gets independent for every memory cell. The control gate 108 is continuously provided in the x-direction and serves as a word line common to a plurality of memory cells. The control gate 108 and the charge-storage layers 105 are formed in pattern in self-alignment manner so that the side ends thereof are aligned in the y-direction. Then, the control gate 108 is provided with an n-type diffused layer 6 in self-alignment. The memory cell is covered with an inter-layer insulating film 109, and bit lines 110 extending in the y-direction are arranged on the layer 109.
An execution of a data reprogramming process of the EEPROM involves applying a high electric field to between the substrate and the charge-storage layer, to allow a tunnel current to flow through between the charge-storage layer and the substrate, thus modulating a stored charge quantity of the charge-storage layer. A threshold level of the memory cell becomes higher with a larger quantity of negative charge existing within the charge-storage layer, whereas lower with a larger quantity of positive charge existing therein. Accordingly, electron injection into the charge-storage layer raises the threshold level (which may be, e.g., a programming state). On the contrary, pulling out of the electrons from the charge-storage layer lowers the threshold level (which may be, e.g., a data erasing state).
The most important parameter for the data reprogramming of the memory cell described above is a ratio C1/C2 of a capacitance C1 between the charge-storage layer 105 and the substrate 101 to a capacitance C2 between the control gate 108 and the charge-storage layer 105. With the substrate set at an electric potential of 0, when a voltage Vcg is applied to the control gate 108, a voltage Vfg of the charge-storage layer 105 is given such as Vfg=C2·Vcg/(C1+C2). Accordingly, a voltage applied to the tunnel insulating film 104 is determined by a coupling ratio K=C2/(C1+C2)=1/{1+(C1/C2)}.
A generation of a tunnel current requires applying an electric field as high as several tens of MV/cm to the tunnel insulating film. It is required for attaining this that the high voltage Vfg on the order of 10V be applied to between the charge-storage layer and the substrate. The charge-storage layer is coupled to the control gate by capacitance-coupling; hence a high voltage of approximately 20V is needed as the voltage Vcg=K·Vfg to be applied to the control gates. Even when the same voltage is applied to the control gates, if the coupling ratio K is different, the voltage applied to the tunnel insulating film becomes different, to attain different threshold levels for the memory cell. This causes an expansion of a threshold value distribution in the programming state of the memory cell. It is therefore of importance to uniformize the coupling ratio K.
FIG. 3 shows dimensions of the respective elements of the conventional memory cell structure. A capacitance ratio C2/C1 is obtained by using these dimensions in the following formula:C2/C1={Wa+2(d+Tsti++Wing)}Tox/Wa·TonoWing=(Wsti−SL)/2
The capacitance C2 is determined by a face-to-face area between the charge-storage layer 105 and the control gate 108. Hence, variation in the capacitance C2 is caused by variation in thickness of the charge-storage layer and variation in a length Wing (which is so-called a Wing length) of an overhang into the isolation region of the charge-storage layer 105.
Further, there is a high possibility in which the thickness of the charge-storage layer 105 is not uniform as shown in FIG. 3 when the device forming area and the isolation region have different heights. The non-uniformity of the thickness of the charge-storage layer leads to variation in an effective surface areal size of the charge-storage layer. This is also a factor for causing variation in the capacitance C2.
The wing length Wing is determined by an isolation width Wsti and a cut width (a so-called slit width) SL of the charge-storage layer. Cell miniaturization in order to increase the capacity of the EEPROM and decrease the cost thereof, often results in the dimensions of the isolation width Wsti and the slit width SL becoming the minimum width among those decided when the memory cells have been manufactured. In the memory cell described previously, the slit width SL of the charge-storage layer 105 is smaller than the isolation width Wsti and is therefore the minimum dimension. The isolation width in combination with the device forming area, however, determines a pitch of the bit lines, and it is therefore desired that the isolation width Wsti be set small to the greatest possible degree in order to shrink the memory cell array area.
A method utilizing the side-wall remaining technique has already been proposed by the present inventors (K. Shimizu et al. '97IEDM) for achieving a small slit width falling within the range of the small isolation width and smaller than this isolation width. According to this method, the masking material for slit processing is formed in pattern on the charge-storage layer, and thereafter an additional masking material is deposited with the side wall remaining, thereby obtaining a small slit width. FIGS. 4A to 4E show the memory cell manufacturing process described above.
As shown in FIG. 4A, gate material layers 105a are deposited on a silicon substrate 101 through a gate insulating film 104, and masking materials 201 are provided on the layers 105a, thus making a pattern formation so that the gate material layers 105a are left on the device forming area. Then, as illustrated in FIG. 4B, isolation trenches are formed by etching the substrate 101 by use of the masking materials 201, and the isolation insulating films 102 are embedded into these trenches. Subsequently, as shown in FIG. 4C, the gate material layers 105a are deposited again, and masking materials 202 for slit processing are formed in pattern on the isolation insulating films 102.
Further, as shown in FIG. 4D, masking materials 203 are deposited thin and left on only side walls of the masking materials 202 by an isotropic dry etching. A slit-processing window smaller than the minimum processing dimension is thereby formed. Then, gate material layers 105 bare etched by using the masking materials 202 and 203, where by the charge-storage layer 105 taking the stacked structure of the gate material layers 105a and 105b is isolated by the isolation insulating films 102 and thus formed in pattern. Thereafter, as shown in FIG. 4E, a control gate 108 is provided via the inter-gate insulating film 107. The control gate 108 is, as described above, subjected to the isolation processing in the bit-line direction together with the charge-storage layer 105.
According to the method described above, however, after executing the slit processing to isolate the charge-storage layer by etching the gate material layers 105b in the process in FIG. 4D, the surfaces of the isolation insulating films 102 are etched in the process of removing the masking materials 202 and 203 by etching, and, as shown in FIG. 4E, narrow trenches 204 are formed in slit separating portions of the charge-storage layer 105. The trenches 204 formed in the surfaces of the isolation insulating films 102 continuously extend in the bit-line direction the y-direction in FIG. 1) as well as being formed in the section in FIG. 4E wherein the control gate 108 is provided. This trench 204 is extremely narrow, and therefore, deposition of the materials of the inter-gate insulating film 107 and of the control gate 108 to fill these trenches 204, produces etching residues along the trenches 204 in the patterning process thereof. This might cause a gate short-circuit accident. Further, the thickness of the isolation insulating film 102 just under the control gate 108 decreases, and hence, a thin isolation insulating film 102 lowers an isolation function.
As discussed above, in the EEPROM including the memory cells based on the stacked structure of the charge-storage layer and the control gate, with the hyperfine structure of the device, there exists a problem in which a data reprogramming performance declines due to variation in capacitance-coupling that is caused by the ununiformity of the thickness of the charge-storage layer and by variation in descent width of the slit for separating the charge-storage layer. Another problem is that when executing the processing of the slit narrower than the isolation width on the isolation insulating film for separating the charge-storage layers, a layer reduction of the isolation insulating film occurs, and an gate-to-gate short-circuit accident is caused due to deterioration of the isolation performance and the gate residues as well.
Discussed next are well-known structures of several types of memory cells and their disadvantages.
FIGS. 5A and 5B show a first well-known example of memory cell having a STI (Shallow Trench Isolation) structure. FIG. 5A is a plan view, and FIG. 5B is a sectional view taken along the line A–A′ in FIG. 5A.
As shown, isolation trenches 302 are formed in a p-type silicon substrate or p-well 301. Each trench 302 is filled with an isolation material, such as, silicon dioxide. Formed on the entire surface of an element region (channel region) 308 on the substrate that has been subjected to isolation is a thin tunnel-insulating film 4 through which a tunnel current will flow, and a charge-storage layer 5 thereon. Moreover, a control gate 307 is formed on the charge-storage layer 305 via a gate-to-gate insulating film 306. It is shown in FIG. 5B that bottom portions 305a of the charge-storage layer 305 protrude downwardly along the isolation trenches 2.
FIGS. 6A to 6D are sectional views each illustrating a step of manufacturing the STI-cell structure shown in FIGS. 5A and 5B.
As illustrated in FIG. 6A, a dummy insulating film 310 is formed on the semiconductor substrate 301, and a masking material 311, such as, photoresist, is deposited on the insulating film 310. The masking material 311, dummy insulating film 310 and substrate 301 in the isolation region are etched by photolithography so that their side walls are flush with each other to form the trenches 2.
The surface of the trench-side wall is oxidized by thermal oxidation with appropriate requirements. The thermal oxidation results in a “bird's beak” structure formed at each dummy insulating film 310, with the masking material 311 as a mask against the oxidation. The “bird's beak” structure is thicker than an oxide film formed at each trench side wall, thus resulting in a round edge at each trench.
An isolation insulating film is deposited on the entire surface of the semiconductor substrate to fill the trenches 320 with an isolation insulating film 3. The upper surface of the insulating film 303 is polished, or etched back by dry etching or polished by chemical-mechanical polishing (CMP), thus the upper surface of the masking material 311 being exposed (FIG. 6B).
The masking material 311 and the dummy insulating film 310 are peeled off by dry etching or wet etching with chemicals, and a tunnel insulating film 304 and a charge-storage layer 305 are deposited thereon (FIG. 6C).
The charge-storage layer 305 is patterned into slits by lithography on the isolation region, and the gate-to-gate insulating film 306 and the control gate 307 are deposited thereon with gate formation by pattering to finish fabrication of the cell structure (FIG. 6D).
Discussed next with a memory cell operation is the reason for the bottom portions 305a of the charge-storage layer 305 protruding downwardly along the isolation trenches 302.
Data programming to a memory cell having such a tunnel oxide film is performed by modulation of charges stored in the charge-storage layer 5 by charge transfer between the layer 305 and the substrate 301. At least either charge-injection or charge-discharging is performed with FN (Fowler-Nordheim) tunneling. In detail, a high electric filed at 10 MV/cm or more is applied to between the charge-storage layer 305 and the substrate 301 to discharge electrons from the former to the latter or from the latter to the former. The electron discharging will not change the charges stored in the charge-storage layer 305 unless there is no data reprogramming because it is in a complete floating state.
High-voltage application to the charge-storage layer 305 requires voltage application to the control gate 307 for capacitance-coupling therebetween. A high voltage to the control gate, however, forces several transistors that constitute a voltage regulator for generating such a high voltage, input/output switching circuitry, and so on, to have high withstand voltages, thus resulting in a large element region.
A voltage Vfg to be applied to the tunnel insulating film 304 is given by the following expression:Vfg=C2/(C1+C2)Vcgwhere C1 and C2 represent the capacitance between the charge-storage layer 305 and the semiconductor substrate 301 via the tunnel insulating film 304 and that between the charge-storage layer 305 and the control gate 307 via the gate-to-gate insulating film 306, respectively; and Vcg represents a control gate voltage.
As is apparent from the expression that a higher capacitance C2, that is, the capacitance between the charge-storage layer 305 and the control gate 307 via the gate-to-gate insulating film 306, is efficient to lower the voltage to be applied to the control gate 307. A high capacitance C2 can be attained with a large area for the control gate 307 and charge-storage layer 305 facing each other, which is achieved by forming the layer 305 as protruding from the element region to the isolation region as already discussed.
The second well-known memory cell structure described above, however, has two major drawbacks.
The first drawback lies in difficulty attaining a miniaturized width for isolation. Cutting the charge-storage layer 305 into slits on the isolation region requires microfabrication for the slits narrower than widths of the element region and isolation region. Lithography is generally used for slit formation. However, slit formation on the isolation region requires a pattern arrangement such that slit patterns will not overlap the isolation region located thereunder even though the slit patterns displace due to lithography. This results in a wide isolation width even slit patterns are formed as narrower than the isolation width. It is concluded that the well-known memory cell structure fabricated with slit formation using lithography for charge-storage layers has difficulty in miniaturization of isolation region.
The second drawback lies in difficulty attaining a miniaturized width for device areas. The well-known memory cell structure could have an exposed trench side wall during wat etching for peeling off the dummy isolation film. Such an exposed trench side wall produces a parasitic MOS capacitance between the side wall and the charge-storage layer via the tunnel isolation film as already discussed. The smaller the rounded trench side wall end, the worse the cut-off characteristics for the memory cell transistors due to generation of the kink characteristics in the sub-threshold range. Moreover, data-programming by FN-tunneling electron injection with a high voltage to the control gate generates gate electric field mostly on the parasitic MOS capacitance, thus causing dielectric breakdown to the tunnel isolation film.
A further rounded trench side wall can protect the tunnel isolation film from dielectric breakdown. A trench sidewall with excess oxidation for rounding, however, forms a bird's beak at the side wall as discussed above, thus producing an element region width extremely narrower compared when the trench is formed. This requires patterns wide enough for canceling width reduction due to oxidation for rounding of the trench side wall. Moreover, the larger the bird's beak, the more the variation in size thereof, thus causing difficulty in control of miniaturized device size.
As discussed above, the second well-known STI memory cell structure has drawbacks on miniaturization of the isolation width and element region width.
FIGS. 7A and 7B illustrate the second well-known STI structure introduced in the Japanese Un-examined Patent Publication 10-017948 as one example of a STI structure for solving the problems discussed above. FIG. 7A is a plan view and FIG. 7B is a sectional view taken along the line B–B′.
As shown, isolation trenches 2 are formed in a p-type silicon substrate or p-well 301. Each trench 302 is filled with an isolation insulating material 303, such as, silicon dioxide. Formed on the entire surface of the channel region on the substrate that has been subjected to isolation is a thin tunnel-insulating film 304 through which a tunnel current will flow. Formed on the tunnel-insulating film 304 is a charge-storage layer 312, the side wall thereof meeting the end of the isolation region. The isolation insulating film 303 touches the charge-storage layer 312. A portion of the side wall of the charge-storage layer 312 is exposed and faces a control gate 314 via a gate-to-gate insulating film 313 to increase capacity between the charge-storage layer 312 and the control gate 314. The charge-storage layer 312 and the control gate 314 are formed by self-alignment in the vertical direction so that their side walls are flush with each other. An n-type diffused layer 309 is formed between the gates.
FIGS. 8A to 8D are sectional views each illustrating a step of manufacturing the STI-cell structure shown in FIGS. 7A and 7B.
A conductive material 312 that will become a charge-storage layer and a masking material 315 are deposited over the semiconductor substrate 301 via the tunnel-insulating film 304. The masking material 315, the conductive material 312, the tunnel-insulating film 304 and the semiconductor substrate 301 in the isolation region are etched so that their side walls are flush with each other to form trenches 302 (FIG. 8A).
The surface of the trench-side wall is oxidized by thermal oxidation with appropriate requirements before deposition of the isolation insulating film 303. The upper surface of the insulating film 303 is polished, or etched back by dry etching or polished by chemical-mechanical polishing (CMP), thus the upper surface of the masking material 315 being exposed (FIG. 8B).
The isolation insulating film 303 is further etched back to expose a side-wall portion of the charge-storage layer 312, followed by peeling-off the masking material 315 (FIG. 8C).
The gate-to-gate insulating film 313 and the control gate 314 are deposited thereon with gate formation by pattering to finish fabrication of the cell structure (FIG. 8D).
The third well-known STI-cell structure requires no dummy isolation film like the first well-known STI-cell structure. This is because, in the second well-known STI-cell structure, the tunnel-insulating film and the charge-storage layer are deposited before formation of the trenches with the isolation insulating film filled therein. The second well-known structure has no exposed trench-side wall, thus suitable for miniaturization of element region width.
Moreover, this STI-cell structure requires no formation of the charge-isolation layer into slits on the isolation region because it is completely isolated thereon, thus achieving miniaturization of isolation region width in this respect.
On the other hand, the second well-known STI-cell structure has difficulty in miniaturization of isolation region width with respect to a high aspect of trenches filled with the isolation insulating film. As described, the first well-known STI-cell structure has a large area of the charge-storage layer that faces the control gate with a portion of the charge-storage layer protruding along the isolation insulating film. Contrary to this, the second well-known structure attains a large area of the charge-storage layer with its side-wall portion facing the control gate, thus requiring a charge-storage layer thick enough for facing the control gate.
Suppose that an aspect ratio is 2 for an isolation insulating film with no voids when buried into a 0.3 μm-deep trench with a 0.15 μm-thick charge-storage layer. Under the requirements, a 0.275 μm-wide isolation width is offered for burying an insulating film via 0.1 μm-thick masking material; whereas the first well-known STI-cell structure offers 0.2 μm-wide isolation width at a low aspect because of not so narrow charge-storage layer when embedding an insulating film. The second well-known STI-cell structure has restriction of isolation width due to embedding an isolation insulating film, not to slit formation to the charge-storage layer.
As discussed above, a non-volatile semiconductor memory device with the well-known STI-cell structure has difficulty in miniaturization of element region width and isolation width, thus causing restriction of miniaturization of memory cells.